1. Field
Exemplary embodiments of the present invention relate to a memory device, and more particularly, to a refresh technology of a memory device.
2. Description of the Related Art
A memory cell of a memory device includes a transistor serving as a switch and a capacitor for storing charge (data). A logic ‘high’ (logic 1) and a logic ‘low’ (logic 0) of data are determined according to whether charge exists in the capacitor in the memory cell, that is, whether a terminal voltage of the capacitor is high or low.
Since the storage of data represents that charge is accumulated in the capacitor, there is no power consumption in an ideal condition. However, since the initial amount of charge stored in the capacitor is removed due to leakage current caused by PN junction and the like of a MOS transistor, data may be lost. In order to substantially prevent this concern, it is necessary to read data in the memory cell before the data is lost, and to recharge a normal charge amount based on the read information. Only when such an operation is periodically repeated, the storage of data is substantially maintained. Such a recharge process of cell charge will be called a refresh operation.
The refresh operation is performed whenever a refresh command is applied from a memory controller to the memory device, wherein the memory controller applies the refresh command to the memory device at a predetermined time interval in consideration of a data retention time of the memory device. For example, in the case in which all memory cells in the memory device may be refreshed only when the data retention time of the memory device is 64 ms and the refresh command is applied 8000 times, the memory controller applies the refresh command to the memory device 8000 times for 64 ms. Meanwhile, in a test process of the memory device, a memory device having a data retention time less than a prescribed time is processed as fail. The memory device processed as fail is discarded.